You might think non-blocking assignments run in parallel — surprise! Thanks to the scheduler, they politely wait their turn and execute in sequence, giving the illusion of parallelism.
Ever wondered why $display, $strobe, and $monitor show different values at the same simulation time in Verilog?
The answer lies in the unsung hero of simulation: the Event Scheduler.
Let’s decode it — region by region
Active Region – The First Responder
Executes blocking assignments (=), if, case, and $display
RHS of non-blocking assignments (<=) also evaluated here
Pro Tip: Runs in the order written — but doesn’t update NBAs yet!
Inactive Region – The #0 Delay Slot
Executes zero-delay #0 statements
Comes right after active region but before any NBA updates
Pro Tip: Use with caution — can lead to race conditions if overused
NBA Region – The Safe Updater
Applies non-blocking assignments (<=)
Captures values early, updates them later
Pro Tip: Ensures parallel, race-free register transfers
Postponed Region – The Observer
Handles $monitor, $strobe, and assertions
Runs after all updates — shows final signal values
Pro Tip: Use for clean, stable output and debugging
This was the core of my recent Verilog deep-dive — from concepts to code to waveform output.
Slides attached for a closer look.
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