In the world of ASIC/FPGA design, efficient verification is paramount.
That's why I'm thrilled to unveil our new Automated Simulation Regression System!
This project is all about making your Verification Life Easier:
for Verilog, SystemVerilog, and UVM
only just provide Testcase name and seed numbers in Excel sheet. with vital metrics:
how many tests ran, passed, failed, and any errors or warnings.
by automating repetitive tasks, allowing engineers to focus on innovation.
Extracts critical metrics (pass, fail, error, fatal, warnings) and consolidates them into intuitive HTML reports.
Designed to handle large volumes of test cases and rapid feedback.
Github : https://lnkd.in/dyePzT9W
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